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| Preliminary K6F1616U6M Family Document Title 1M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM CMOS SRAM Revision History Revision No. History 0.0 0.1 Initial draft Revise - Change package type : from FBGA to TBGA Draft Date August 22, 2000 November 21, 2000 Remark Preliminary Preliminary The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 0.1 November 2000 Preliminary K6F1616U6M Family FEATURES * Process Technology: Full CMOS * Organization: 1M x16 * Power Supply Voltage: 2.7~3.3V * Low Data Retention Voltage: 1.5V(Min) * Three state output * Package Type: 48-TBGA-9.00x12.00 CMOS SRAM GENERAL DESCRIPTION The K6F1616U6M families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. 1M x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM PRODUCT FAMILY Power Dissipation Product Family K6F1616U6M-F Operating Temperature Industrial(-40~85C) Vcc Range 2.7~3.3V Speed 551)/70ns Standby (ISB1, Typ.) 2A Operating (ICC1, Max) 4mA PKG Type 48-TBGA-9.00x12.00 1. The parameter is measured with 30pF test load. 2. Typical value are measured at VCC=3.0V, TA=25C and not 100% tested. PIN DESCRIPTION 1 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. A LB OE A0 A1 A2 CS2 Vcc Vss B I/O9 UB A3 A4 CS1 I/O1 Row Addresses C Row select I/O10 I/O11 A5 A6 I/O2 I/O3 Memory Cell Array D Vss I/O12 A17 A7 I/O4 Vcc Data cont Data cont Data cont I/O Circuit Column select E Vcc I/O13 Vss A16 I/O5 Vss I/O1~I/O8 F I/O9~I/O16 I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 A19 A12 A13 WE I/O8 Column Addresses H A18 A8 A9 A10 A11 DNU CS1 48-TBGA: Top View (Ball Down) CS2 OE WE Control Logic Name CS1, CS2 OE WE A0~A19 Function Chip Select Inputs Output Enable Input Write Enable Input Address Inputs Name Vcc Vss UB LB DNU Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) Do Not Use UB LB I/O1~I/O16 Data Inputs/Outputs SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 0.1 November 2000 Preliminary K6F1616U6M Family PRODUCT LIST Industrial Temperature Products(-40~85C) Part Name K6F1616U6M-EF55 K6F1616U6M-EF70 Function 48-TBGA, 55ns, 3.0V 48-TBGA, 70ns, 3.0V CMOS SRAM FUNCTIONAL DESCRIPTION CS1 H X1) X1) L L L L L L L L CS2 X 1) OE X 1) WE X 1) LB X 1) UB X 1) I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active L X1) H H H H H H H H X1) X1) H H L L L X1) X 1) X1) X1) H H H H H L L L X1) H L X 1) X1) H X 1) L H L L H L L L H L L H L X1) 1. X means dont care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V(Max. 3.6V) -0.2 to 3.6 1.0 -65 to 150 -40 to 85 Unit V V W C C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 0.1 November 2000 Preliminary K6F1616U6M Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.23) Typ 3.0 0 - CMOS SRAM Max 3.3 0 Vcc+0.22) 0.6 Unit V V V V Note: 1. TA=-40 to 85C, otherwise specified 2. Overshoot: VCC+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol Test Conditions VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH, VIO=Vss to Vcc Cycle time=1s, 100%duty, IIO=0mA, CS10.2V, LB0.2V or/and UB0.2V, CS2Vcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA Other input =0~Vcc 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0VCS20.2V(CS2 controlled) or 3) LB=UBVcc-0.2V, CS2Vcc-0.2V(LB/UB controlled) 70ns 55ns Min -1 -1 2.4 Typ1) - Max 1 1 4 35 40 0.4 - Unit A A mA mA V V A ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage VOL VOH Standby Current (CMOS) ISB1 - 2.0 40 1. Typical value are measured at VCC=3.0V, TA=25C and not 100% tested. 4 Revision 0.1 November 2000 Preliminary K6F1616U6M Family AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL CMOS SRAM VTM3) R12) CL1) R22) 1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V AC CHARACTERISTICS (Vcc=2.7~3.3V, TA=-40 to 85C) Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output LB, UB valid to data output Read Chip select to low-Z output Output enable to low-Z output LB, UB enable to low-Z output Output hold from address change Chip disable to high-Z output OE disable to high-Z output UB, LB disable to high-Z output Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write pulse width Write Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z LB, UB valid to end of write tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tOLZ tBLZ tOH tHZ1, tHZ2 tOHZ tBHZ tWC tCW1, tCW2 tAS tAW tWP tWR tWHZ tDW tDH tOW tBW 55 10 5 10 10 0 0 0 55 45 0 45 40 0 0 25 0 5 45 55ns Max 55 55 25 55 20 20 20 20 Min 70 10 5 10 10 0 0 0 70 60 0 60 50 0 0 30 0 5 60 70ns Max 70 70 35 70 25 25 25 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V1), VIN0V Vcc=1.5V, CS1Vcc-0.2V , VIN0V See data retention waveform 1) Min 1.5 0 tRC Typ 1.0 2) Max 3.3 15 - Unit V A ns 1. 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0CS20.2V(CS2 controlled) or 3) LB=UBVcc-0.2V, CS2Vcc-0.2V(LB/UB controlled) 2. Typical value are measured at TA=25C and not 100% tested. 5 Revision 0.1 November 2000 Preliminary K6F1616U6M Family TIMMING DIAGRAMS CMOS SRAM TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL) tRC Address tOH Data Out Previous Data Valid tAA Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tOH CS1 CS2 tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ Data out High-Z NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 0.1 November 2000 Preliminary K6F1616U6M Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS1 tWR(4) CMOS SRAM CS2 tAW tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH High-Z UB, LB TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z 7 Revision 0.1 November 2000 Preliminary K6F1616U6M Family TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) CS1 tAW CS2 UB, LB tBW tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4) CMOS SRAM Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high. DATA RETENTION WAVE FORM CS1, LB/UB controlled VCC 2.7V tSDR Data Retention Mode tRDR 2.2V VDR CS1VCC - 0.2V, LB=UBVCC - 0.2V CS1,LB/UB GND CS2 controlled VCC 2.7V CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS20.2V 8 Revision 0.1 November 2000 Preliminary K6F1616U6M Family PACKAGE DIMENSION 48 BALL TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View Bottom View B B B1 CMOS SRAM Unit: millimeters A1 INDEX MARK 0.65 0.65 6 A #A1 B C D 5 4 3 2 1 C1 E C1/2 F G H B/2 Detail A A 0.35/Typ. Y 0.55/Typ. Notes. 1. Bump counts: 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) Side View D C Min A B B1 C C1 D E E1 E2 Y 8.90 11.90 0.40 0.80 0.30 - Typ 0.75 9.00 3.75 12.00 5.25 0.45 0.90 0.55 0.35 - Max 9.10 12.10 0.50 1.00 0.40 0.08 C 9 Revision 0.1 November 2000 C E2 E1 E |
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